1. Field of Invention
This invention relates to the field of digital to analog converters (DACs) operating at intermediate or radio frequencies often used in direct digital synthesizers or for comparators and DACs in the feedback path of Analog to Digital Converters (ADCs).
2. Description of the Related Art
DACs convert a digital input, for example an 8 bit word, to an analog voltage amplitude. A digital 8 bit word such as 10101010 is converted by a DAC to its analog equivalent. The actual amplitude corresponding to an input such as 10101010 is relative to the maximum amplitude, or full scale, for a particular system.
One requirement of DAC conversion is that linearity be preserved over time as well as over the full conversion range. Linearity means that the analog signal amplitude output from the DAC will be exactly 1/(256xe2x88x921) of full scale higher for a digital input of 10101011 as compared to an input of 10101010, or between any other digital inputs separated by one (least significant) bit. Another aspect of linearity is that the output voltage generated by a digital input of 01111111 should be half of the maximum voltage generated by a digital input of 11111111. For good linearity, the voltage output of the DAC should follow a straight line as the digital input goes from 00000000 to its maximum 11111111.
One typical approach of converting a digital word into an analog amplitude is to activate switches, typically transistors, within the DAC for each of the xe2x80x9c1xe2x80x9d bits presented from the input binary digital word. In one implementation, each transistor switch connects a current source feeding an R/2R branch of a resistive ladder. The resulting current from a plurality of R/2R branches is fed into a current to voltage converter to obtain the output voltage of the DAC corresponding to the digital input.
An alternate method of conversion is to have (256xe2x88x921) unit weighted current sources switched in response to a digital input to a current summer and current to voltage converter. If the characteristics of each of the (256xe2x88x921) current sources is well controlled, the DC linearity, matched dynamic or transient response is improved.
Using a R/2R resistor, or thermometer coded or unit weighted methods of current summation for digital input to voltage conversion creates errors. One source of error is self heating of each of the transistor switches activated by the digital input words. As the frequency of digital to analog conversion increases, self heating becomes more prevalent as a source of error. This error is further aggravated during the generation of symmetrical waveforms, such as sine or triangle waves typically used in digital frequency synthesizers. In generating such symmetrical waveforms, the ON time of certain digital input bits descriptive of the sine and triangle waves will have a larger duty cycle as compared to other input bits. In effect, some of the transistor switches activated by the digital inputs will stay on longer than others. This longer on time will induce self heating in some transistor switches, but less in others. Because of this differential self heating, some transistors will operate at a different temperature, thus operating point, introducing errors in the Digital to Analog conversion process. The thermal dependence of transistor parameters on temperature is well known.
With the reduction of transistor size due to high frequency operation, thermal resistance from the transistor heat source to a heat sink is increased. This reduction in the path of heat dissipation further aggravates the differential self heating. With increasing operating frequency, as the temperatures of switching transistors increases, so does the differential self heating among switching transistors forming a DAC. As a consequence, undesirable non-linear, temperature dependent operation is encountered.
In the prior art, one approach to differential heating has been achieved by reducing the power dissipation in the switching transistors. This limits the dynamic range or signal to noise ratio because the signal level at the DAC output is reduced.
Yet another approach in thermometer coded or unit weighted (unary) weighted current switches is to use matched transistors having matched VBE voltages for DAC switches thereby reducing the effect of differential self heating. Typically, paralleling requires binary to thermometer decode logic ahead of the DAC current switches. For an 8 bit DAC, (256xe2x88x921) transistors are required to equally share the current load. The 256xe2x88x921 current switches tend to reduce differential heating because of the similarity of transistor structures. This takes up chip real-estate as the number of bits of resolution increases.
For high resolution DACs, the binary input word is often partitioned into two sub-words, a most significant word (MSW) and a Least Significant Word (LSW). The MSW uses thermometer code while the LSW uses R-2R binary code.
Yet another approach to provide self heating compensation uses VBE differential control of the operating point of the switching transistors so as to offset the errors due to self heating. This type of complex analog circuitry increases parts count as a tradeoff for better self heating compensation while still subject to matching limitations.
All above methods for reducing the effects of differential heating are analog in nature and have side effects that are undesirable reducing DAC speed and linearity.
Differential heating is avoided by a digital to analog converter for generating analog cyclical waveforms having a period. The cyclical waveforms are generated by conversion of a sequence of step wise linearly incrementing digital phase words presented during the period for conversion. The combination of digital logic with a DAC is often used with a Direct Digital Synthesizer or a waveform generator.
The digital to analog converter for cyclical wave applications comprises:
a) A clock for operating conversion timing within the digital to analog converter. The clock generates a clock pulse for conversion of each of the digital phase words by said digital to analog converter while generating the cyclical waveform.
b) A lookup read only memory for converting each of the incrementing digital phase words within the period into a plurality of ON commands to be used by a plurality of current sources, said plurality of ON commands timed to generate said cyclical waveforms, said ON commands having equal time duration.
c) A first exclusive - OR circuit having a first input, a second input and an output, said first input connected to said sequence of ON commands from said lookup table, said sequence of ON commands generated using a second exclusive OR circuit and a unary decoder, said second input connected to said incrementing digital phase words, said output connected to a register buffer.
d) The register buffer is for storing said output from said exclusive - OR circuit for the duration of each clock cycle.
e) The register buffer drives the current sources thereby activating each of the current sources for equal time intervals during the period.
f) A summer for summing the current sources into a sum of currents.
g) A current to voltage converter for converting the sum of currents into an output voltage, the output voltage generating said cyclical waveform.
The cyclical waveform has one or more non-linear portions reflected in the content of the read only memory.
The invention applies to unary and R-2R partitioned DACs without loss of generality.